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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
Rev. 01 -- 14 February 2006 Product data sheet
1. General description
The PCA9506 provides 40-bit parallel input/output (I/O) port expansion for I2C-bus applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable of sourcing 10 mA and sinking 25 mA with a total package load of 800 mA to allow direct driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output. Output ports are totem-pole and their logic state changes at the Acknowledge (bank change). The device can be configured to have each input port to be masked in order to prevent it from generating interrupts when its state changes and to have the I/O data logic state to be inverted when read by the system master. An open-drain interrupt (INT) output pin allows monitoring of the input pins and is asserted each time a change occurs in one or several input ports (unless masked). The Output Enable (OE) pin 3-states any I/O selected as output and can be used as an input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle). The internal Power-On Reset (POR) or hardware reset (RESET) pin initializes the 40 I/Os as inputs. Three address select pins configure one of 8 slave addresses. The PCA9506 is available in 56-pin TSSOP and HVQFN packages and is specified over the -40 C to +85 C industrial temperature range.
2. Features
s Standard mode (100 kHz) and Fast mode (400 kHz) compatible I2C-bus serial interface s 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os s 40 configurable I/O pins that default to inputs at power-up s Outputs: x Totem-pole (10 mA source, 25 mA sink) with controlled edge rate output structure x Active LOW output enable (OE) input pin 3-states all outputs x Output state change on Acknowledge s Inputs: x Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs x Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change x Polarity Inversion register allows inversion of the polarity of the I/O pins when read s Active LOW reset (RESET) input pin resets device to power-up default state s 3 programmable address pins allowing 8 devices on the same bus
Philips Semiconductors
PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
s Designed for live insertion x Minimize line disturbance (IOFF and power-up 3-state) x Signal transient rejection (50 ns noise filter and robust I2C-bus state machine) s Low standby current s -40 C to +85 C operation s ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 s Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA s Offered in TSSOP56 and HVQFN56 packages
3. Applications
s s s s s s s s Servers RAID systems Industrial control Medical equipment PLCs Cell phones Gaming machines Instrumentation and test measurement
4. Ordering information
Table 1: Ordering information Topside mark PCA9506DGG PCA9506BS Package Name PCA9506DGG PCA9506BS TSSOP56 HVQFN56 Description plastic thin shrink small outline package; 56 leads; body width 6.1 mm plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm Version SOT364-1 SOT684-1 Type number
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Product data sheet
Rev. 01 -- 14 February 2006
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Philips Semiconductors
PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
5. Block diagram
OE
PCA9506
A0 A1 A2 8-bit INPUT/ OUTPUT PORTS BANK 0 BANK 1 SCL SDA LOW PASS INPUT FILTERS I2C-BUS CONTROL BANK 2 BANK 3 8-bit
write pulse 0 read pulse 0
IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7
write pulse 4 VDD VSS RESET POWER-ON RESET read pulse 4
INPUT/ OUTPUT PORTS BANK 4
IO4_0 IO4_1 IO4_2 IO4_3 IO4_4 IO4_5 IO4_6 IO4_7
INTERRUPT MANAGEMENT INT LP FILTER
002aab492
All I/Os are set to inputs at power-up and RESET.
Fig 1. Block diagram of PCA9506
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Product data sheet
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
configuration port register data (Cx[y]) I/O configuration register data from shift register write configuration pulse D Q VDD CK Q IOx_y data from shift register ESD protection diode VSS write pulse CK output port register input port register D Q output port register data (Ox[y])
D
Q
Mx[y] INTERRUPT MANAGEMENT
INT
input port register data (Ix[y])
read pulse
CK polarity inversion register
data from shift register write polarity pulse
D
Q
polarity register data (Px[y])
002aab493
CK
On power-up or RESET, all registers return to default values.
Fig 2. Simplified schematic of IO0_0 to IO4_7
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
6. Pinning information
6.1 Pinning
SDA SCL IO0_0 IO0_1 IO0_2 VSS IO0_3 IO0_4 IO0_5
1 2 3 4 5 6 7 8 9
56 RESET 55 INT 54 IO4_7 53 IO4_6 52 IO4_5 51 VSS 50 IO4_4 49 IO4_3 48 IO4_2 47 IO4_1 46 VDD 45 IO4_0 44 IO3_7 43 IO3_6 42 IO3_5 41 IO3_4 40 IO3_3 39 VSS 38 IO3_2 37 IO3_1 36 IO3_0 35 IO2_7 34 VSS 33 IO2_6 32 IO2_5 31 IO2_4 30 OE 29 A2
002aab491
IO0_6 10 VSS 11 IO0_7 12 IO1_0 13 IO1_1 14 IO1_2 15 IO1_3 16 IO1_4 17 VDD 18 IO1_5 19 IO1_6 20 IO1_7 21 IO2_0 22 VSS 23 IO2_1 24 IO2_2 25 IO2_3 26 A0 27 A1 28
PCA9506DGG
Fig 3. Pin configuration for TSSOP56
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Philips Semiconductors
PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
49 RESET
56 IO0_3
54 IO0_2
53 IO0_1
52 IO0_0
47 IO4_7
46 IO4_6
45 IO4_5
terminal 1 index area IO0_4 IO0_5 IO0_6 VSS IO0_7 IO1_0 IO1_1 IO1_2 IO1_3 1 2 3 4 5 6 7 8 9
43 IO4_4 42 IO4_3 41 IO4_2 40 IO4_1 39 VDD 38 IO4_0 37 IO3_7 36 IO3_6 35 IO3_5 34 IO3_4 33 IO3_3 32 VSS 31 IO3_2 30 IO3_1 29 IO3_0 IO2_7 28
002aab975
50 SDA
51 SCL
55 VSS
PCA9506BS
IO1_4 10 VDD 11 IO1_5 12 IO1_6 13 IO1_7 14 IO2_0 15 VSS 16 IO2_1 17 IO2_2 18 IO2_3 19 A0 20 A1 21 A2 22 OE 23 IO2_4 24 IO2_5 25 IO2_6 26 VSS 27
Transparent top view
Fig 4. Pin configuration for HVQFN56
6.2 Pin description
Table 2: Symbol SDA SCL IO0_0 to IO0_7 IO1_0 to IO1_7 IO2_0 to IO2_7 IO3_0 to IO3_7 IO4_0 to IO4_7 VSS VDD A0 A1 A2
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Pin description Pin TSSOP56 1 2 3, 4, 5, 7, 8, 9, 10, 12 13, 14, 15, 16, 17, 19, 20, 21 22, 24, 25, 26, 31, 32, 33, 35 36, 37, 38, 40, 41, 42, 43, 44 45, 47, 48, 49, 50, 52, 53, 54 6, 11, 23, 34, 39, 51 18, 46 27 28 29 HVQFN56 50 51 I/O I serial data line serial clock line input/output bank 0 input/output bank 1 input/output bank 2 input/output bank 3 input/output bank 4 ground supply voltage supply voltage address input 0 address input 1 address input 2
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Type
Description
52, 53, 54, 56, 1, I/O 2, 3, 5 6, 7, 8, 9, 10, 12, I/O 13, 14 15, 17, 18, 19, 24, 25, 26, 28 29, 30, 31, 33, 34, 35, 36, 37 38, 40, 41, 42, 43, 45, 46, 47 I/O I/O I/O
4, 16, 27, 32, 44, power 55 [1] supply 11, 39 20 21 22 power supply I I I
Product data sheet
Rev. 01 -- 14 February 2006
44 VSS
48 INT
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Philips Semiconductors
PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
Pin description ...continued Pin TSSOP56 HVQFN56 23 48 49 I O I active LOW output enable input active LOW interrupt output active LOW reset input 30 55 56 Type Description
Table 2: Symbol OE INT RESET
[1]
HVQFN package die supply ground is connected to both VSS pins and exposed center pad. VSS pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
7. Functional description
Refer to Figure 1 "Block diagram of PCA9506" and Figure 2 "Simplified schematic of IO0_0 to IO4_7".
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA9506 is shown in Figure 5. Slave address pins A2, A1, and A0 choose 1 of 8 slave addresses and need to be connected to VDD (1) or VSS (0). To conserve power, no internal pull-up resistors are incorporated on A2, A1, and A0.
slave address 0 1 0 0 A2 A1 A0 R/W
fixed
programmable
002aab494
Fig 5. PCA9506 address
The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation.
7.2 Command register
Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9506, which will be stored in the Command register.
AI 1
- 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0 default at power-up or after RESET
register number Auto-Increment
002aab495
Fig 6. Command register
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Product data sheet
Rev. 01 -- 14 February 2006
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Philips Semiconductors
PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
The lowest 6 bits are used as a pointer to determine which register will be accessed. The registers are:
* * * * *
IP: Input Port registers (5 registers) OP: Output Port registers (5 registers) PI: Polarity Inversion registers (5 registers) IOC: I/O Configuration registers (5 registers) MSK: Mask interrupt registers (5 registers)
If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically incremented after a read or write. This allows the user to program and/or read the 5 register banks sequentially. If more than 5 bytes of data are written and AI = 1, previous data in the selected registers will be overwritten. Reserved registers are skipped and not accessed (refer to Table 3). If the Auto-Increment flag is cleared (AI = 0), the 3 least significant bits are not incremented after data is read or written. During a read operation, the same register bank is read each time. During a write operation, data is written to the same register bank each time. Only a Command register code with the 5 least significant bits equal to the 25 allowable values as defined in Table 3 are valid. Reserved or undefined command codes must not be accessed for proper device functionality. At power-up, this register defaults to 0x80, with the AI bit set to logic 1, and the lowest 7 bits set to logic 0. During a write operation, the PCA9506 will acknowledge a byte sent to OPx, PIx, and IOCx and MSKx registers, but will not acknowledge a byte sent to the IPx registers since these are read-only registers.
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
7.3 Register definitions
Table 3: Register # (hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Register summary D5 D4 D3 D2 D1 D0 Symbol Access Description
Input Port registers 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 IP0 IP1 IP2 IP3 IP4 OP0 OP1 OP2 OP3 OP4 PI0 PI1 PI2 PI3 PI4 IOC0 IOC1 IOC2 IOC3 IOC4 read only read only read only read only read only read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write read/write Input Port register bank 0 Input Port register bank 1 Input Port register bank 2 Input Port register bank 3 Input Port register bank 4 reserved for future use reserved for future use reserved for future use Output Port register bank 0 Output Port register bank 1 Output Port register bank 2 Output Port register bank 3 Output Port register bank 4 reserved for future use reserved for future use reserved for future use Polarity Inversion register bank 0 Polarity Inversion register bank 1 Polarity Inversion register bank 2 Polarity Inversion register bank 3 Polarity Inversion register bank 4 reserved for future use reserved for future use reserved for future use I/O Configuration register bank 0 I/O Configuration register bank 1 I/O Configuration register bank 2 I/O Configuration register bank 3 I/O Configuration register bank 4 reserved for future use reserved for future use reserved for future use
Output Port registers
Polarity Inversion registers
I/O Configuration registers
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Product data sheet
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
Table 3: Register # (hex) 20 21 22 23 24 25 26 27
Register summary ...continued D5 D4 D3 D2 D1 D0 Symbol Access Description
Mask Interrupt registers 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MSK0 MSK1 MSK2 MSK3 MSK4 read/write read/write read/write read/write read/write Mask Interrupt register bank 0 Mask Interrupt register bank 1 Mask Interrupt register bank 2 Mask Interrupt register bank 3 Mask Interrupt register bank 4 reserved for future use reserved for future use reserved for future use
7.3.1 IP0 to IP4 - Input Port registers
These registers are read-only. They reflect the incoming logic levels of the port pins regardless of whether the pin is defined as an input or an output by the I/O Configuration register. If the corresponding Px[y] bit in the PI registers is set to logic 0, or the inverted incoming logic levels if the corresponding Px[y] bit in the PI register is set to logic 1. Writes to these registers have no effect.
Table 4: IP0 to IP4 - Input Port registers (address 00h to 04h) bit description Legend: * default value `X' determined by the externally applied logic level. Address 00h 01h 02h 03h 04h Register IP0 IP1 IP2 IP3 IP4 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol I0[7:0] I1[7:0] I2[7:0] I3[7:0] I4[7:0] Access R R R R R Value XXXX XXXX* XXXX XXXX* XXXX XXXX* XXXX XXXX* XXXX XXXX* Description Input Port register bank 0 Input Port register bank 1 Input Port register bank 2 Input Port register bank 3 Input Port register bank 4
The Polarity Inversion register can invert the logic states of the port pins. The polarity of the corresponding bit is inverted when Px[y] bit in the PI register is set to logic 1. The polarity of the corresponding bit is not inverted when Px[y] bits in the PI register is set to logic 0.
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
7.3.2 OP0 to OP4 - Output Port registers
These registers reflect the outgoing logic levels of the pins defined as outputs by the I/O Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the values that are in the flip-flops controlling the output selection, not the actual pin values. Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0). Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0). Where `x' refers to the bank number (0 to 4); `y' refers to the bit number (0 to 7).
Table 5: OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description Legend: * default value. Address 08h 09h 0Ah 0Bh 0Ch Register OP0 OP1 OP2 OP3 OP4 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol O0[7:0] O1[7:0] O2[7:0] O3[7:0] O4[7:0] Access R/W R/W R/W R/W R/W Value 0000 0000* 0000 0000* 0000 0000* 0000 0000* 0000 0000* Description Output Port register bank 0 Output Port register bank 1 Output Port register bank 2 Output Port register bank 3 Output Port register bank 4
7.3.3 PI0 to PI4 - Polarity Inversion registers
These registers allow inversion of the polarity of the corresponding Input Port register. Px[y] = 0: The corresponding Input Port register data polarity is retained. Px[y] = 1: The corresponding Input Port register data polarity is inverted. Where `x' refers to the bank number (0 to 4); `y' refers to the bit number (0 to 7).
Table 6: PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description Legend: * default value. Address 10h 11h 12h 13h 14h Register PI0 PI1 PI2 PI3 PI4 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol P0[7:0] P1[7:0] P2[7:0] P3[7:0] P4[7:0] Access R/W R/W R/W R/W R/W Value 0000 0000* 0000 0000* 0000 0000* 0000 0000* 0000 0000* Description Polarity Inversion register bank 0 Polarity Inversion register bank 1 Polarity Inversion register bank 2 Polarity Inversion register bank 3 Polarity Inversion register bank 4
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
7.3.4 IOC0 to IOC4 - I/O Configuration registers
These registers configure the direction of the I/O pins. Cx[y] = 0: The corresponding port pin is an output. Cx[y] = 1: The corresponding port pin is an input. Where `x' refers to the bank number (0 to 4); `y' refers to the bit number (0 to 7).
Table 7: IOC0 to IOC4 - I/O Configuration registers (address 18h to 1Ch) bit description Legend: * default value. Address 18h 19h 1Ah 1Bh 1Ch Register IOC0 IOC1 IOC2 IOC3 IOC4 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol C0[7:0] C1[7:0] C2[7:0] C3[7:0] C4[7:0] Access R/W R/W R/W R/W R/W Value 1111 1111* 1111 1111* 1111 1111* 1111 1111* 1111 1111* Description I/O Configuration register bank 0 I/O Configuration register bank 1 I/O Configuration register bank 2 I/O Configuration register bank 3 I/O Configuration register bank 4
7.3.5 MSK0 to MSK4 - Mask interrupt registers
These registers mask the interrupt due to a change in the I/O pins configured as inputs. `x' refers to the bank number (0 to 4); `y' refers to the bit number (0 to 7). Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input (Cx[y] in IOC register = 1). Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined as input (Cx[y] in IOC register = 1).
Table 8: MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit description Legend: * default value. Address 20h 21h 22h 23h 24h Register MSK0 MSK1 MSK2 MSK3 MSK4 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol M0[7:0] M1[7:0] M2[7:0] M3[7:0] M4[7:0] Access R/W R/W R/W R/W R/W Value 1111 1111* 1111 1111* 1111 1111* 1111 1111* 1111 1111* Description Mask Interrupt register bank 0 Mask Interrupt register bank 1 Mask Interrupt register bank 2 Mask Interrupt register bank 3 Mask Interrupt register bank 4
7.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9506 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9506 registers and I2C-bus state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
7.5 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9506 registers and I2C-bus state machine will be held in their default states until the RESET input is once again HIGH.
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
7.6 Interrupt output (INT)
The open-drain active LOW interrupt is activated when one of the port pins changes state and the port pin is configured as an input and the interrupt on it is not masked. The interrupt is deactivated when the port pin input returns to its previous state or the Input Port register is read. Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. Only a Read of the Input Port register that contains the bit(s) image of the input(s) that generated the interrupt clears the interrupt condition. If more than one input register changed state before a read of the Input Port register is initiated, the interrupt is cleared when all the input registers containing all the inputs that changed are read. Example: If IO0_5, IO2_3, and IO3_7 change state at the same time, the interrupt is cleared only when INREG0, INREG2, and INREG3 are read.
7.7 Output enable input (OE)
The active LOW output enable pin allows to enable or disable all the I/Os at the same time. When a LOW level is applied to the OE pin, all the I/Os configured as outputs are enabled and the logic value programmed in their respective OP registers is applied to the pins. When a HIGH level is applied to the OE pin, all the I/Os configured as outputs are 3-stated. For applications requiring LED blinking with brightness control, this pin can be used to control the brightness by applying a high frequency PWM signal on the OE pin. LEDs can be blinked using the Output Port registers and can be dimmed using the PWM signal on the OE pin thus controlling the brightness by adjusting the duty cycle.
7.8 Live insertion
The PCA9506 is fully specified for live insertion applications using IOFF, power-up 3-states, robust state machine, and 50 ns noise filter. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state's circuitry places the outputs in the high-impedance state during power-up and power-down, which prevents driver conflict and bus contention. The robust state machine does not respond until it sees a valid START condition and the 50 ns noise filter will filter out any insertion glitches. The PCA9506 will not cause corruption of active data on the bus, nor will the device be damaged or cause damage to devices already on the bus when similar featured devices are being used.
7.9 Standby
The PCA9506 goes into standby when the I2C-bus is idle. Standby supply current is lower than 1 A (typical).
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 7).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 7. Bit transfer
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 8).
SDA
SDA
SCL S START condition P STOP condition
SCL
mba608
Fig 8. Definition of START and STOP conditions
8.2 System configuration
A device generating a message is a `transmitter'; a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 9).
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER
SLAVE
002aaa966
Fig 9. System configuration
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement
002aaa987
9
Fig 10. Acknowledgement on the I2C-bus
8.4 Bus transactions
Data is transmitted to the PCA9506 registers using Write Byte transfers (see Figure 11, Figure 12, and Figure 13). Data is read from the PCA9506 registers using Read and Receive Byte transfers (see Figure 14).
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Rev. 01 -- 14 February 2006
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Product data sheet Rev. 01 -- 14 February 2006
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. 9397 750 14939
Philips Semiconductors
STOP condition slave address command register DATA BANK 0 acknowledge from slave A DATA BANK 1 acknowledge from slave A DATA BANK 2 acknowledge from slave A DATA BANK 3 acknowledge from slave A DATA BANK 4 acknowledge from slave AP
SDA S 0 1 0 0 A2 A1 A0 0 A 1 0 0 0 1 0 0 0 A START condition R/W acknowledge from slave AI = 1 output bank register bank 0 is selected acknowledge from slave
write to port
data out from port tv(Q)
data valid bank 0
data valid bank 1
data valid bank 2
data valid bank 3
data valid bank 4
002aab496
OE is LOW to observe a change in the outputs. If more than 5 bytes are written, previous data are overwritten.
Fig 11. Write to the 5 output ports
40-bit I2C-bus I/O port with RESET, OE, and INT
slave address SDA S 0 1 0 0 A2 A1 A0 0 A AI 0 0 0 1 D2 D1 D0 A START condition R/W acknowledge from slave write to port acknowledge from slave DATA BANK X AP
acknowledge STOP from slave condition
data out from port tv(Q)
data X valid
PCA9506
002aab497
OE is LOW to observe a change in the outputs. Two, three, or four adjacent banks can be programmed by using the Auto-Increment feature (AI = 1) and change at the corresponding output port becomes effective at each acknowledge.
16 of 30
Fig 12. Write to a specific output port
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Product data sheet Rev. 01 -- 14 February 2006
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. 9397 750 14939
Philips Semiconductors
slave address
command register DATA BANK 0 A DATA BANK 1 A DATA BANK 2 A DATA BANK 3 A DATA BANK 4 AP
SDA S 0 1 0 0 A2 A1 A0 0 A 1 0 D5 D4 D3 D2 D1 D0 A START condition R/W acknowledge from slave AI = 1
acknowledge from slave
acknowledge from slave
acknowledge from slave
D[5:0] = 01 0000 for Polarity Inversion register programming bank 0 D[5:0] = 01 1000 for Configuration register programming bank 0 D[5:0] = 10 0000 for Mask Interrupt register programming bank 0
acknowledge from slave acknowledge from slave
acknowledge from slave STOP condition
002aab498
The programming becomes effective at the acknowledge. Less than 5 bytes can be programmed by using this scheme. D5, D4, D3, D2, D1, D0 refers to the first register to be programmed. If more than 5 bytes are written, previous data are overwritten (the sixth Configuration register will roll over to the first addressed Configuration register, the sixth Polarity Inversion register will roll over to the first addressed Polarity Inversion register and the sixth Mask Interrupt register will roll over to the first addressed Mask Interrupt register).
Fig 13. Write to the I/O Configuration, Polarity Inversion or Mask Interrupt registers
slave address
command register
repeated START condition slave address
At this moment master-transmitter becomes master-receiver, and slave-receiver becomes slave-transmitter. (cont.)
SDA S 0 1 0 0 A2 A1 A0 0 A 1 0 D5 D4 D3 D2 D1 D0 A Sr 0 1 0 0 A2 A1 A0 1 A START condition R/W acknowledge from slave AI = 1 acknowledge from slave
40-bit I2C-bus I/O port with RESET, OE, and INT
R/W acknowledge from slave
D[5:0] = 00 0000 for Input Port register bank 0 D[5:0] = 00 1000 for Output Port register bank 0 D[5:0] = 01 0000 for Polarity Inversion register bank 0 D[5:0] = 01 1000 for Configuration register bank 0 D[5:0] = 10 0000 for Mask Interrupt register bank 0 acknowledge from master data from register A DATA last byte AP STOP condition no acknowledge from master
data from register DATA first byte register determined by D[5:0]
acknowledge from master data from register A DATA second byte
002aab499
PCA9506
If AI = 0, the same register is read during the whole sequence. If AI = 1, the register value is incremented after each read. When the last register bank is read, it rolls over to the first byte of the category (see category definition in Section 7.2 "Command register"). The INT signal is released only when the last register containing an input that changed has been read. For example, when IO2_4 and IO4_7 change at the same time and an Input Port register's read sequence is initiated, starting with IP0, INT is released after IP4 is read (and not after IP2 is read).
17 of 30
Fig 14. Read from Input Port, Output Port, I/O Configuration, Polarity Inversion or Mask Interrupt registers
Philips Semiconductors
PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
9. Application design-in information
5V
1.6 k 1.6 k 1.1 k (optional) 2 k 1.1 k (optional)
VDD VDD MASTER CONTROLLER SCL SDA RESET INT OE GND VDD
SUB-SYSTEM 1 (e.g., temp sensor) INT IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 B IO1_0 IO3_7 A2 A1 A0 VSS IO4_0 IO4_7 VDD SUB-SYSTEM 3 (e.g., alarm system) ALARM ENABLE SUB-SYSTEM 2 (e.g., counter) RESET A controlled switch (e.g., CBT device)
PCA9506
SCL SDA RESET INT OE
ALPHA NUMERIC KEYPAD
24 LED MATRIX
002aab500
Device address configured as 0100 000X for this example. IO0_0, IO0_2, IO0_3, IO1_0 to IO3_7 are configured as outputs. IO0_1, IO0_4, IO4_0 to IO4_7 configured as inputs.
Fig 15. Typical application
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
10. Limiting values
Table 9: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI II VI/O(n) VI/O(IO0n) IO(I/On) IDD ISS Ptot Tstg Tamb Tj Parameter supply voltage input voltage input current input/output voltage on any other pin input/output voltage on pin IO0_n output current on an I/O pin supply current ground supply current total power dissipation storage temperature ambient temperature junction temperature operating operating storage Conditions Min -0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 -20 -65 -40 Max +6 5.5 20 5.5 5.5 +50 500 1100 500 +150 +85 125 150 Unit V V mA V V mA mA mA mW C C C C
11. Static characteristics
Table 10: Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supply VDD IDD supply voltage supply current operating mode; no load; fSCL = 400 kHz VDD = 2.3 V VDD = 3.3 V VDD = 5.5 V Istb standby current no load; fSCL = 0 kHz; I/O = inputs; VI = VDD VDD = 2.3 V VDD = 3.3 V VDD = 5.5 V VPOR VIL VIH IOL IL Ci power-on reset voltage [1] LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance VOL = 0.4 V VI = VDD = VSS VI = VSS no load; VI = VDD or VSS Input SCL; input/output SDA -0.5 0.7VDD 20 -1 5 +0.3VDD 5.5 +1 10 V V mA A pF 0.15 0.25 0.75 1.70 11 12 15.5 2.0 A A A V 56 98 225 95 150 300 A A A 2.3 5.5 V Parameter Conditions Min Typ Max Unit
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
Table 10: Static characteristics ...continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol I/Os VIL VIH IOL LOW-level input voltage HIGH-level input voltage LOW-level output current VOL = 0.5 V VDD = 2.3 V VDD = 3.0 V VDD = 4.5 V IOL(tot) VOH total LOW-level output current HIGH-level output voltage VOL = 0.5 V; VDD = 4.5 V IOH = -10 mA VDD = 2.3 V VDD = 3.0 V VDD = 4.5 V ILIH ILIL Ci Co IOL IOH Co VIL VIH ILI Ci VIL VIH ILI Ci
[1]
Parameter
Conditions
Min -0.5 2 10 12 15 1.6 2.3 4.0 -1 -1 -
Typ 6 6 3.0 3.0 3.5
Max +0.8 5.5 0.6 +1 +1 7 7 +1 5 +0.8 5.5 +1 5 +0.3VDD 5.5 +1 5
Unit V V mA mA mA A V V V A A pF pF mA A pF V V A pF V V A pF
HIGH-level input leakage current LOW-level input leakage current input capacitance output capacitance LOW-level output current HIGH-level output current output capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance
VDD = 3.6 V; VI = VDD VDD = 5.5 V; VI = VSS
Interrupt INT VOL = 0.4 V 6 -1 -0.5 2 -1 -0.5 0.7VDD -1 -
Inputs RESET and OE
Inputs A0, A1, A2
VDD must be lowered to 0.2 V in order to reset part.
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40-bit I2C-bus I/O port with RESET, OE, and INT
12. Dynamic characteristics
Table 11: Symbol Dynamic characteristics Parameter Conditions Standard mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time [2] data valid time [3] data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter enable time disable time data output valid time data input setup time data input hold time valid time on pin INT_N reset time on pin INT_N reset pulse width reset recovery time reset time output output
[4] [5] [1]
Fast mode I2C-bus Min 0 1.3 0.6 0.6 0.6 0 0.1 0.1 100 1.3 0.6 20 + 0.1Cb
[6]
Unit
Max 100 3.45 3.45 300 1000 50
Max 400 0.9 0.9 300 300 50 kHz s s s s ns s s ns s s ns ns ns
0 4.7 4.0 4.7 4.0 0 0.1 0.1 250 4.7 4.0 -
[4] [5]
20 + 0.1Cb [6] -
[7]
Port timing ten tdis tv(Q) tsu(D) th(D) tv(INT_N) trst(INT_N) Reset tw(rst) trec(rst) trst
[1] [2] [3] [4]
100 0.5 4 0 100
80 40 250 4 4 -
100 0.5 4 0 100
80 40 250 4 4 -
ns ns ns ns s s s ns ns ns
Interrupt timing
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region SCL's falling edge.
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
[5]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. Cb = total capacitance of one bus line in pF. Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
[6] [7]
SDA tBUF tLOW SCL tr tf tHD;STA tSP
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
002aaa986
Fig 16. Definition of timing on the I2C-bus
protocol
START condition (S) tSU;STA
bit 7 MSB (A7) tLOW tHIGH
bit 6 (A6)
bit 0 (R/W)
acknowledge (A)
STOP condition (P)
1/f
SCL
SCL tBUF tr tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab175
Rise and fall times refer to VIL and VIH.
Fig 17. I2C-bus timing diagram
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Philips Semiconductors
PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
START SCL
ACK or read cycle
SDA 30 % trst RESET 50 % trec(rst) tw(rst) trst IOx_y 50 % output off
002aac018
50 %
50 %
Fig 18. Reset timing
13. Test information
2VDD open VSS
VDD PULSE GENERATOR VI DUT
RT
VO
RL 500
CL 50 pF
500
002aac019
RL = load resistance CL = load capacitance includes jig and probe capacitance RT = termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 19. Test circuitry for switching times
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
14. Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1
D
E
A
X
c y HE vMA
Z
56
29
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp wM
28
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 14.1 13.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.5 0.1 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 20. Package outline SOT364-1 (TSSOP56)
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm
SOT684-1
D
B
A
terminal 1 index area E
A A1 c
detail X
e1 e 15 L 14
1/2 e
C b 28 29 e vMCAB wMC y1 C y
Eh
1/2 e
e2
1 terminal 1 index area 56 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 8.1 7.9 Dh 4.45 4.15 E(1) 8.1 7.9 Eh 4.45 4.15 e 0.5 43
42 X 2.5 scale e1 6.5 e2 6.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT684-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 21. Package outline SOT684-1 (HVQFN56)
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
15. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under "Handling MOS devices".
16. Soldering
16.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
16.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
16.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
16.5 Package related soldering information
Table 12: Package [1] BGA, LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8],
[1]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave Reflow [2] suitable suitable not suitable not suitable [4]
HTSSON..T [3],
suitable not WQCCN..L [8] recommended [5] [6] not recommended [7] not suitable
suitable suitable suitable not suitable
PMFP [9],
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office.
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40-bit I2C-bus I/O port with RESET, OE, and INT
[2]
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[3]
[4]
[5] [6] [7] [8]
[9]
17. Abbreviations
Table 13: Acronym CDM DUT ESD HBM IC I2C-bus LED MM PLC POR PWM RAID Abbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Human Body Model Integrated Circuit Inter IC bus Light Emitting Diode Machine Model Programmable Logic Controller Power-On Reset Pulse Width Modulation Redundant Array of Independent Disks
18. Revision history
Table 14: Revision history Release date 20060214 Data sheet status Product data sheet Change notice Doc. number 9397 750 14939 Supersedes Document ID PCA9506_1
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40-bit I2C-bus I/O port with RESET, OE, and INT
19. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
20. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
22. Trademarks
Notice -- All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of Koninklijke Philips Electronics N.V.
21. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
23. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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40-bit I2C-bus I/O port with RESET, OE, and INT
24. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.1.1 8.2 8.3 8.4 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 Command register . . . . . . . . . . . . . . . . . . . . . . 7 Register definitions . . . . . . . . . . . . . . . . . . . . . . 9 IP0 to IP4 - Input Port registers . . . . . . . . . . . 10 OP0 to OP4 - Output Port registers . . . . . . . . 11 PI0 to PI4 - Polarity Inversion registers. . . . . . 11 IOC0 to IOC4 - I/O Configuration registers. . . 12 MSK0 to MSK4 - Mask interrupt registers . . . 12 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 12 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 13 Output enable input (OE) . . . . . . . . . . . . . . . . 13 Live insertion . . . . . . . . . . . . . . . . . . . . . . . . . 13 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Characteristics of the I2C-bus. . . . . . . . . . . . . 14 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 START and STOP conditions . . . . . . . . . . . . . 14 System configuration . . . . . . . . . . . . . . . . . . . 14 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 15 Application design-in information . . . . . . . . . 18 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19 Static characteristics. . . . . . . . . . . . . . . . . . . . 19 Dynamic characteristics . . . . . . . . . . . . . . . . . 21 Test information . . . . . . . . . . . . . . . . . . . . . . . . 23 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 Handling information. . . . . . . . . . . . . . . . . . . . 26 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 27 Package related soldering information . . . . . . 27 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 19 20 21 22 23 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 29 29 29 29 29
(c) Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 February 2006 Document number: 9397 750 14939
Published in The Netherlands

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